Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption
نویسندگان
چکیده
This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.
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ورودعنوان ژورنال:
- IEICE Electronic Express
دوره 10 شماره
صفحات -
تاریخ انتشار 2013